1. Field of The Invention
In the present invention, a semiconductor device which is suitable for the high integration is suggested, and the manufacturing method thereof is disclosed. The semiconductor device in accordance with the present invention is particularly used for a non-volatile memory device having a floating gate.
2. Description of The Prior Art
A lot of research development relating to the finer structure and higher integration of semiconductor device have been under progress. Above all, the achievement of refining technique of insulated gate field effect semiconductor device which is called MOSFET is remarkable. The word MOS represent the initials of Metal-Oxide-Semiconductor. The metal means not only pure metal but also a semiconductor material of sufficiently large conductivity as well as the alloy of semiconductor and metal, in wider definition. Besides a pure oxide film, the insulator such as nitride film can be used instead of the oxide film of metal and semiconductor, and in which case, the terminology of MOS is not necessarily appropriate, however, the field effect device having these kind of structures, including nitride and the other insulators, are called MOSFET or MOS transistor, in the present description.
In a normal MOS transistor, an oxide film (insulator) such as silicon oxide, is formed on a semiconductor surface as a gate oxide film (insulated gate film), on which a metal or semiconductor and the like which works as a gate electrode, is provided, and by controlling the electric potential of the gate electrode, the conductivity of the semiconductor of a base, is controlled.
When a semiconductor film which is electrically independent (floating gate) is formed on the gate oxide film, and another insulated film is formed thereupon, so as to provide a gate electrode (control gate), it is conventionally known that this can be used as a device of non-volatile memory. The memory having such a structure is commercially sold as EPROM or EEPROM. The basic idea of this memory is to fix the conductivity of the semiconductor of the base semipermanently by applying strong electric field to a control gate electrode, and whereby trapping a charge such as electron and hole on an intermediate floating gate film, and by having this electrified in a specific conductive mode. In a case that the charge injected in the floating gate is removed by means of the irradiation of ultraviolet or by some electric effect, the initial state is recovered, i.e. a certain data is erased. The MOS transistor having the floating gate of this kind is utilized as a memory cell transistor.
Since a power source is not needed for the memory utilizing this kind of device to retain memory, which is not the case with RAM such as DRAM or SRAM, and a capacitor is not needed, in particular, in comparison with the DRAM, when a memory of no less than 16 M bit is to be manufactured, the cell area per bit can be reduced, which fact means higher integration, and the research relating to this field has recently become even more intense. The EEPROM with which an erasing operation can be carried out electrically, in particular, has drawn much attention.
When higher integration is to be achieved, however, there are a number of problems remain to be solved under current situation. When a memory device is to be manufactured using this kind of device, the memory cannot be formed out of the device only, but a selective transistor has to be formed along with the device. The structure of the EEPROM of the most advanced high integration of prior arts is shown in FIG. 2(A). Referring to the figure, 201 is a source region, 202, a drain region, 203, a floating gate, and 204 is a control gate. The device is integrated from the viewpoint of structure, however, the area surrounded by dots P in the figure, works as a selective transistor, and the area surrounded by dots C) works as a memory cell transistor from the viewpoint of function.
When a data is to be written into a memory transistor, high voltage (normally not less than 10 V) is applied to the drain 202 and the control gate 204, so as to inject a charge into the floating gate 203, while, in order to erase the data, when a high electric field is applied to the drain, under a condition that the electric potential of the control gate 204 and the source 201 are maintained at the same level, the charge of the floating gate can be extracted. Since the characteristic of insulating film is deteriorated if the writing and erasing operation is repeated too many times, the upper limit of the number of operation is said to be 100,000.
In order to inspect whether there is a data or not, after a normal voltage for operating the MOS transistor, is applied to the drain 202, a normal voltage is applied to the control gate 204. By so doing, the selective transistor P is turned "ON". If a charge (electron(hole), if a semiconductor substrate is P-type (N-type) while source and drain are N-type(P-type)) is trapped on the floating gate of the memory cell transistor Q, since the memory cell transistor is not affected by the electric field of the control gate above, current is not run. When there is no charge in the floating gate, or when the floating gate is electrified instead, since the floating gate is affected by the control gate, and is thus turned "ON", current is run.
The description supra is an example of general EEPROM, while there are some variations according to which is injected into the floating gate, electron or hole, and whether a charge is injected or removed at the time of writing, and the basic concept is to extract the state of a memory cell transistor to the outside through a selective transistor.
In practice, a memory device is put into function only after a lot of devices are provided in line, so as to form a wiring shown in FIG. 2(B). Referring to the figure, X, X' are word lines, and Y, Y' are bit lines. When a specific bit wiring is observed under a condition that any of the word wirings is chosen, a signal is detected when a data is stored in the memory cell transistor on the point where the word line and the bit line are crossed with each other, and when the data is not stored therein, the signal is not detected.
In a simplest model, one of the integrated devices can be used as a memory cell of one bit, however, in order to increase accuracy, two of the same cells are prepared, with a data written into one cell, And no data in the other one, and the signals from these two cells are compared with each other. Namely, if there is a difference in the electric potentials of the signals transmitted from these two cells, it is judged that there is a data, and that there is no data when there is no difference in the electric potentials. Although a memory capacity is reduced to half if this method is adopted, the adoption of this method is preferred to increase accuracy when noise begins to be superimposed on the bit line, as the higher integration is proceeded.
The transistor device of this kind has several problems with regard to high integration. First, as shown in FIG. 2(A), as the width of the device, L.sub.1 +L.sub.2 is a lower limit. The minimum values of L.sub.1 and L.sub.2 represent process accuracy, and in the current technological situation, 0.5 micrometer is a limit when mass productivity is considered.
At least 1 micrometer is thus required for the gate part alone of this device. As this is a critical problem concerning the whole system of the MOS semiconductor device in a broader perspective, it is necessary to provide a contact on a source and drain region, and it is required that the slightly larger area should be allocated for the contact, which is located below the gate part. Namely, the entire device source region is connected into a ground level, or into a power supply line, while a contact of several micrometer of diameter is formed on the drain region, and a metal wiring is crossed with the gate wiring. In this case, the metal wiring should be located on the upper layer of the gate wiring, and should be lead down to the drain region formed on the substrate surface through a hole formed on an interlayer insulating film. For this reason, there is a long distance in the connected part from the contact part to the bit line, and the breaking of the wiring or the contact failure should become an important problem. For example, the technique of burying a contact hole by the CVD deposition of tungsten was worked out to deal with such a problem. If the special technique of burying the contact hole is not to be used, the other techniques of enlarging the area of the contact, of widening the contact hole, or of forming the contact hole into a conical shape, must be needed, however, all of them are reverse ways to high integration.
Next problem is that a self-aligning method is not adopted when an EEPROM is to be manufactured, which results in the increase in the number of mask processes. Practically, for the EEPROM to be operated, it is required when a tunnel current is injected from the drain that the floating gate 203 is superimposed on the drain region 202 to a certain degree. When a planar photolithography technique is adopted to obtain the superimposition, since the displacement of no less than 0.2 micrometer of a photomask must be considered under the current technique, in order to ensure that the drain region is superimposed on the floating gate, the superimposed region of at least 0.4 micrometer is required. If the size of the region is not more than this level, the displacement of the superimposition will be no less than 50%, which will cause a critical problem for the yield of the device.
The manufacturing of the memory region of the conventional EEPROM includes at least the following processes to name only the principal ones. Roman numerals on the far right end are the number of mask processes.
______________________________________ (1) To form a device separate region (LOCOS) on a .cndot..cndot..cndot..cndot..cndot..cndot. 1 semiconductor substrate. (2) To form a drain region 202. .cndot..cndot..cndot..cndot..cndot..cndot. II (3) To form a floating gate. .cndot..cndot..cndot..cndot..cndot..cndot. III (4) To form a control gate (word line). .cndot..cndot..cndot..cndot..cndot..cndot. IV (5) To form a source region 201. (6) To form an interlayer insulator, and to form a .cndot..cndot..cndot..cndot..cndot..cndot. V contact hole on the drain. (7) To form a bit line. .cndot..cndot..cndot..cndot..cndot..cndot. VI ______________________________________
Almost all processes like this need mask process (it is only (5) that does not need a mask, because it can be formed by self-align method), It is required of all of those processes that the accuracy is 0.2 micrometer or less. Therefore, in conclusion, con, pared with DRAM(5 pieces of mask processes), yield decreases.
EEPROM is regarded as a memory element which will replace DRAM in the future as a peculiar non-volatile memory named flash memory. If its yield is high, the unit price by one bit will be relatively expensive and its competitiveness will be weak.